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Embedded Systems Design Lab Report

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Lab 1 Spring 2020 College of Engineering and Computing Department of Electrical and Computer Engineering ECE 387: ​Embedded Systems Design Section A Professor J.D. Kimball Yunhao Ni Qianyi Cheng Chuxiao Zhou Date: February 11, 2020 I. Description of experiments In Lab 1, there are 3 parts of the experiment, including multiplexor, JK flip flop, and pulse width modulation. 1) Multiplexor Goal: Using the DIP switches as input and LED as output to emulate the behavior of a 2×1 multiplexor. The multiplexor can take multiple signals and outputs a single signal which can regard as an electronic switch. A is a select switch, I1 and I0 are input signals and Q is output signal. In our experiment, A is a select switch, and I0 and I1 are two switches work as input signals. Q is the output LED which can demonstrate 0 and 1. By controlling the switches, the result can be compared with the truth table. Fig 1. Truth Table for a 2×1 multiplexor [1]. As we can see in Fig. 2, A, I0, and I1 is assigned from switches 0 to 2 (define the A is 1 when the pointer goes down). Q is assigned to LEDR[0]. Fig. 2. PIN Assignment for Experiment 1. 2) JK Flip Flop Goal: ​Using DIP switches as input, and using LED as output, modulate a J-K Flip Flop, which should be responded with correct timing. As shown in Figure 2, J-K flip flop is a chip that has three inputs J, K, and clock. Input J is set input and input K is reset input. And also this chip has two output Q and Qbar, where Q is the normal output with the logic shown below, and Qbar is like a Qnext that shows the output after clock working, which means it will respond with time. Figure 2. J-K Flip Flop As shown in the truth table below, we can get a result that when the clock work and input J and K have different values (low or high), the output Q will follow the value of J. When J and K are both zero (law), the outputs Q and Q’ will not change. When both J and K are one (high), the output Q and Q’ will toggles from one state to another. All of those situations are working when the input clock is one (high). Figure 3. Truth Table Figure 4 is the PIN assignment for experiment 2. Clk is assigned to a manual clock input. J and K are our input switch signals. Fig. 4. PIN Assignment for Experiment 2. 3) Pulse Width Modulation Goal: Output a 50 Hz square wave PWM signal with a duty cycle varied from 5% to 15% by using the GPIO output pin and DIP input switches. Since the initial frequency counts for 50 MHz, in order to generate a 50 Hz PWM signal, the period should be divided into 1M (1000000). We designed each switch corresponding to one duty cycle. In our experiment, 8 cases (5%-9%, 11%, 13%, 15%) are considered so that we need 3 digits binary numbers to distribute these 8 cases which are from 2 down to 0. For example, for the 5% duty cycle, the initial output is low (0V). The “count” will be increased by 1 each time and when it’s in the range of 1 to 50000, the output signal is high, which means the pulse is on, if not, the output signal is low, which means the pulse is off (0V). The first module lab1_3 will be designed to call the main PWM module. II. Results 1) Multiplexor From the truth table, we can get the logic function and use VHDL to achieve our purpose. The following is our code. library ieee; use ieee.std_logic_1164.all; entity lab1_1 IS port ( A,I1,I0:IN STD_LOGIC; Q: OUT STD_LOGIC); END lab1_1; ARCHITECTURE LogicFunction OF lab1_1 IS BEGIN Q1000000) begin count
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